Through Hole Design of PCB Impedance Controlled

As data communication speeds increase to more than 3 Gbps, signal integrity is critical to the smooth progress of data transmission. Board designers attempt to eliminate every impedance mismatch on the high-speed signal path because these impedance mismatches can cause signal jitter and reduce the degree of data eye opening—making not only the maximum distance for data transmission, but also SONET The margin of general jitter specifications such as (synchronous optical network) or XAUI (10Gb accessory unit interface) is minimized.

Since the signal density on the printed circuit board is increased, more signal transmission layers are required, and transmission through interlayer interconnections (through holes) is also unavoidable. In the past, vias represented an important source of signal distortion because their impedance was typically about 25-35 ohms. Such a large impedance discontinuity reduces the data eye opening by 3 dB and generates a large amount of jitter depending on the data rate. As a result, board designers either try to avoid using vias on high-speed lines or try new technologies such as boring or blind holes. These methods, while useful, add complexity and greatly increase board cost.

A new "coaxial-like" via structure can be utilized to avoid the severe impedance mismatch problem with standard vias. This structure places the ground vias around the signal vias in a special configuration. Through-holes designed using this technique show impedance discontinuities below 4% (50 ± 2 Ω) and improved signal quality on the TDR (Time Domain Reflectometry) curve. This new method produces a vertical channel with adjustable impedance. Developers use a simple coaxial model of the signal line at the center to create this via structure; the surrounding ground shield produces a uniform distribution of impedance. Four ground vias lined up around the center signal via replace the uniform ground shield. Because the four outer vias are connected to the printed circuit board ground or VDD (power), they carry a charge and a capacitance is formed between each of the vias and the signal via. The calculation of the capacitance depends on the via diameter, the dielectric constant, and the distance between the signal via and the ground via. The gap (concave edge) of the central via "touches" the outer via, so the capacitance is evenly distributed along the vertical channel - preventing the capacitance of each power plane and ground plane from increasing dramatically. The outer ground via provides a path for the signal return current and forms an inductive loop between the signal via and the ground via.

Another important design consideration is the size of the pad because each via is connected to the trace and requires a pad. The pad should be as small as possible because the distance from the pad to the ground via is less than the distance from the signal via to the ground via. Due to these pads, the distance is shortened, the capacitance is increased, and the total impedance is lowered.

In a typical design, there are not always four ground vias. As long as the return current has a path from VDD to ground through a nearby bypass capacitor, the via structure has the same good performance as the power via.

For example, consider now a board containing such a via structure in a BGA output pin with a 1 mm grid. Since it is a fixed output pin, you can only ground two external vias; connect the other two vias to VDD. This via structure works well because you can also connect the SMD bypass capacitor between VDD and ground in the BGA.

You can also use this via structure for differential signals. Differential signals can share two external vias, saving board space. Texas Instruments has adopted this approach on the evaluation board of its XAUI transceiver because of the limited space within the BGA of this board. For impedance controlled vias, the size of the interlayer spacing does not matter because the capacitors are formed by ground vias rather than metal layers. However, conventional vias depend on the interlayer capacitance. Therefore, even if the thickness of the board does not change, you must specifically design through holes for different layer stacks.