Case Analysis of Signal Integrity Verification (1)

The same question may get a different answer. The traditional strategy of dealing with potential signal integrity issues in low-speed board designs often involves passive adaptation, which is to develop appropriate design constraints for the design. When some special signal channels have serious signal integrity problems such as signal crosstalk or electromagnetic interference, design engineers often add strict physical constraints to a part of the design or even the entire design itself.

Constraint design typically increases final product cost and constrains product performance. For example, a design engineer may be struggling to find a suitable location to implement a particular signal interconnect and be forced to add a signal plane. However, in today's highly competitive market competition, the ability to achieve the lowest cost and the ability to provide unique product performance often means whether the product is successful or failed.

Many design engineers have found that signal integrity analysis is no longer just a special issue limited to high-speed system design. The real cause of signal integrity problems is the shrinking signal rise time and signal fall time rather than the system clock. As IC manufacturers continue to advance their production process technology, the current technical level has reached 0.25um or even lower. Continuously improving component production technology is used to eliminate outdated technology. When traditional standard electronic components are manufactured using advanced process technology, the size can be made smaller while the switching speed of the device becomes more and more The faster, the shorter the rise and fall times of the signal.

In fact, the size of the transistor gate is reduced by approximately 30% every three years, and accordingly, the switching speed of the transistor is increased by approximately 30%. The reduction in signal rise time and fall time can lead to “potential crises” that ultimately lead to high-speed problems in the design, which have never been seen as a factor in high-speed problems in traditional design flows.

Why is faster signal edge transition (shorter signal rise time and signal fall time) rather than an increase in system clock frequency presenting serious and significant design challenges for board design engineers? This is because when the signal transition is slow (the rise and fall times of the signal are long), the wiring in the PCB can be modeled as an ideal conductor with a certain amount of delay to ensure a fairly high accuracy. For functional analysis, all inline delays can be aggregated at the output of the driver, and the same signal is observed at the same time through the inputs of all receivers connected to the output of the driver through different inline segments. Waveform.

Using the lumped delay parameter model, the circuit behavior can be accurately analyzed without special simulation analysis. Practice has shown that if the delay factor of lumped parameters is taken into account in the design, the physical realization is very close to the theoretical analysis and simulation.

As the signal changes faster (signal rise time and fall time shorten), each routing segment on the board changes from an ideal conductor to a complex transmission line. At this time, the delay of the signal connection can no longer be modeled at the output of the driver in the form of a lumped parameter model. At this point, when the same driver signal drives a complex PCB connection, the signals received on each of the receivers that are electrically coupled together are different. Not only does the signal delay of the entire PCB link need to be split into the signal delays of the separate PCB segments, but the interaction between the various transmission line effects on each PCB segment must be carefully considered. Due to the high speed effects, it is difficult for design engineers to predict signals on complex PCB traces, so transmission line analysis is required to determine the actual delay of the signal at the input of each receiver.

It is known from practical experience that the transmission line utility will be manifested once the length of the transmission line is greater than 1/6 of the effective length of the drive rise time or fall time. For example, suppose the rise time of the components used in the design is 1 ns, and the transmission speed of the signal on the PCB wire is 2 ns/ft. As long as the length of the wire exceeds 1 inch, the transmission line effect occurs, and the potential speed is high. Circuit problems may appear. Obviously, all the wires on the board are less than 1 inch in length and there are fewer and fewer boards. Based on this understanding, it is conceivable that design engineers will encounter high-speed problems when designing components with a rise time of 1 ns.

The above problems have become worse and worse with the continuous upgrading of IC process technology.

In today's system design, devices with a rise time of 1 ns have quickly become a thing of the past. PC design engineers use a high-performance processor with a rise time of 0.5 ns to achieve a clock speed of more than 400 MHz, and the bus's operating frequency has exceeded the complex system design of 100 MHz. These design engineers already have experience in high-speed circuit design and will consider special issues in high-speed design. However, the problem of high-speed design has become more and more popular. When design engineers use new generation FPGA devices with 0.25um process technology or other standard components to design new products, these high-speed problems will be a lot of problems. Exist, the system designed is difficult to work without some types of high-speed analysis.

Signal transitions, rather than the ever-increasing clock frequency in the design, can lead to a deteriorating design environment: smaller and smaller design fault tolerances, and subtle differences in any design can lead to potential problems. One thing that cannot be mentioned here is the recent occurrence of a famous machine vision system manufacturer in the United States. This is a well-known manufacturer of machine vision systems (image detection system manufacturing) in the United States. Recently their board design engineers have encountered a very strange phenomenon. A product that has been successfully designed, manufactured and marketed seven years ago has been able to operate and work very stably and reliably. Recently, products that have been offline from the production line have had problems and the products are not working properly.

This is a 20MHz system design, it seems that there is no need to consider the issue of high-speed design, without any design modifications, the component model used is consistent with the original design requirements. The design engineer felt very confused: Why did the system fail? Without any design modifications, the manufacturing is based on consistent electronic components in the original design. The only difference is that the electronic components used are smaller and faster, thanks to today's evolving IC manufacturing technology. So what is the cause of the system failure?

It turns out that the failure of the system is due to the introduction of signal integrity issues in the new device process technology. These problems are not encountered by design engineers in the original, proven, relatively low-speed systems.