Timing analysis of data setup time

From the first condition, the data signal must arrive at the receiving end before the clock CLKA to properly latch the data. In the common clock bus, the first clock cycle is used to latch data to the output of DRIVER, and the second clock cycle latches the data into RECEIVER, which means that the data signal arrives at the RECEIVER input. Long enough before the clock signal CLKA. In order to meet this condition, it is necessary to determine the delay of the clock and data signals arriving at RECEIVER and to ensure that the setup time of the receiver is met. Any time that is longer than the required setup time is the setup time margin Tmargin. The delay generated by the data signal and the clock signal within the chip or on the transmission line, from the first clock edge to the total delay of the data arriving at the RECEIVER input, the total delay of the received clock CLKA. The total delay from the first clock edge to the arrival of data at the RECEIVER input is:

TDATA_DELAY=TCO_CLKB+Tflt_CLKB+TCO_DATA+Tflt_DATA

The total delay of the next cycle of the receive clock CLKA is:

TCLKA_DELAY=TCYCLE+TCO_CLKA+Tflt_CLKA

To meet the data creation time, you must have:

TCLKA_DELAY_MIN-TDATA_DELAY_MAX-Tsetup-Tmargin>0

Expand and consider the jitter of the clock, Tjitter and other factors to get:

TCYCLE+(TCO_CLKA_MIN-TCO_CLKB_MAX)+ (Tflt_CLKA_MIN-Tflt_CLKB_MAX)-TCO_DATA_MAX-Tflt_DATA_SETTLE_DELAY_MAX-Tjitter-Tsetup-Tmargin>0 (1)

In the formula (1), TCYCLE is one clock cycle of the clock; the first parenthesis is the maximum phase difference between the clock chip CLOCK BUFFER output clocks CLKA and CLKB, which is called the output-output skew in the manual; the second bracket It is the maximum delay difference between the two clocks CLKA and CLKB output by the CLOCK BUFFER chip reaching RECEIVER and DRIVER respectively. TCO_DATA in equation (1) refers to the time interval from the start of the clock trigger to the occurrence of data at the output port and reaching the threshold of the test voltage Vmeas (or VREF) under certain test loads and test conditions. The size of the TCO_DATA and the internal logic delay of the chip. Time, buffer OUTPUT BUFFER characteristics, output load conditions are directly related, TCO can be found in the chip data sheet.

As can be seen from equation (1), the adjustable portion actually has only two items: Tflt_CLKB_MIN-Tflt_CLKB_MAX and Tflt_DATA_SETTLE_DELAY_MAX. Tflt_CLKA_MIN should be as large as possible from the settling time, while Tflt_CLKB_MAX and Tflt_DATA_SETTLE_DELAY_MAX should be as small as possible. In essence, it is required to receive the clock later, and the data comes earlier.