Power integrity design

1. Power distribution system

Power integrity design is a very complicated matter, but how to control the impedance between the power system (power and ground plane) in recent years is the key to the design. In theory, the lower the impedance between power supply systems, the lower the impedance, the smaller the noise amplitude, and the smaller the voltage loss. In the actual design, we can determine the target impedance we want to achieve by specifying the maximum voltage and power supply range. Then, by adjusting the relevant factors in the circuit, the impedance (frequency-dependent) target impedance of each part of the power system is approached.

2. Ground rebound

When the edge rate of a high-speed device is less than 0.5 ns, the data exchange rate from the large-capacity data bus is particularly fast, and when it generates strong ripples in the power supply layer that are sufficient to affect the signal, power supply instability occurs. When the current through the ground loop changes, a voltage is generated due to the loop inductance. When the rising edge is shortened, the current change rate increases, and the ground bounce voltage increases. At this point, the ground plane (ground) is no longer an ideal zero level, and the power supply is not the ideal DC potential. When the gate of the simultaneous switch increases, the ground bounce becomes more severe. For a 128-bit bus, there may be 50_100 I/O lines switching on the same clock edge. At this time, the inductance of the power supply and the ground return that is fed back to the I/O driver that is switched at the same time must be as low as possible. Otherwise, a voltage brush will appear at the standstill connected to the same ground. Ground bounce can be seen everywhere, such as chip, package, connector or circuit board may rebound, resulting in power integrity issues.

From a technology perspective, the rising edge of the device will only decrease, and the width of the bus will only increase. The only way to keep ground bounced is to reduce the power and ground distribution inductance. For the chip, it means moving to an array of wafers, placing the power and ground as much as possible, and the wiring to the package is as short as possible to reduce inductance. For packaging, it means moving the layer package to make the ground plane spacing of the power supply closer, as used in BGA packages. For connectors, it means using more ground pins or redesigning the connectors to have internal power and ground planes, such as connector-based ribbon cords. For a board, it means that the adjacent power and ground planes are as close as possible. Since the inductance is proportional to the length, making the connection of the power supply and ground as short as possible will reduce the ground noise.

3. Decoupling capacitor

We all know that adding some capacitor between the power supply and ground can reduce the noise of the system, but how much capacitor is added to the circuit board? What is the appropriate value of each capacitor? Where is the location of each capacitor better? Similar to these problems, we generally have not seriously considered it. It is only based on the experience of the designer. Sometimes we even think that the smaller the capacitor, the better. In high-speed design, we must consider the parasitic parameters of the capacitor, quantitatively calculate the number of decoupling capacitors and the capacitance of each capacitor and the specific position of the placement, to ensure that the impedance of the system is within the control range, a basic principle Is the need for decoupling capacitors, one can not be less, the excess capacitor, one does not.