PCB Design Guidelines for Ensuring Signal Integrity

1. SI problem

As IC output switching speeds increase, almost all designs encounter signal integrity issues regardless of signal period. Even if you haven't encountered SI problems in the past, as the circuit's operating frequency increases, you will definitely encounter signal integrity problems in the future.

Signal integrity problems mainly refer to signal overshoot and damped oscillations, which are mainly a function of IC drive amplitude and transition time. That is, even if the wiring topology does not change, as long as the chip speed becomes fast enough, the existing design will be in a critical state or stop working. We use two examples to illustrate that signal integrity design is inevitable.

In the communications field, cutting-edge telecommunications companies are producing high-speed boards (above 500MHz) for voice and data exchange, where the cost is not particularly important, so multi-layer boards can be used as much as possible. Such a board can be sufficiently grounded and easily form a power supply loop, or a large number of discrete termination devices can be used as needed, but the design must be correct and not critical.

SI and EMC experts are required to simulate and calculate before wiring. Then, the board design can follow a series of very strict design rules. In case of doubt, the termination device can be added to obtain as much SI safety margin as possible. the amount. During the actual working process of the circuit board, there will always be some problems. For this reason, the SI problem can be avoided by using the controllable impedance terminal wiring. In short, the ultra-standard design can solve the SI problem.

The general SI design guidelines for the design process are described below.

2. Preparation before design

Before the design begins, you must think about and determine the design strategy to guide things such as component selection, process selection, and board production cost control. In the case of SI, research is conducted in advance to form planning or design guidelines to ensure that the design results do not exhibit significant SI problems, crosstalk or timing issues. Some design guidelines can be provided by IC manufacturers. However, the guidelines provided by chip vendors (or your own design guidelines) have limitations that may not be designed to meet the SI requirements. If the design rules are easy, there is no need for a design engineer.

Before actually wiring, first solve the following problems. In most cases, these problems will affect the board you are designing (or considering designing). If the number of boards is large, this work is valuable.

3. Cascading of boards

Some project teams have a lot of autonomy in determining the number of PCB layers, while others do not have this autonomy. Therefore, it is important to know where you are. Interacting with manufacturing and cost analysis engineers can determine the stacking error of the board, and it is a good opportunity to find board manufacturing tolerances. For example, if you specify a layer with 50Ω impedance control, how does the manufacturer measure and ensure this value?

Other important questions include: What are the expected manufacturing tolerances? What is the expected insulation constant on the board? What is the allowable error of line width and spacing? What is the allowable error in the thickness and spacing of the ground plane and signal layer? All of this information can be used during the pre-wiring phase.

Based on the above data, you can choose to cascade. Note that almost every PCB that plugs into other boards or backplanes has thickness requirements, and most board manufacturers have fixed thickness requirements for different types of layers that they can make, which will greatly limit the number of final stacks. . You may want to work closely with the manufacturer to define the number of cascading. Impedance control tools should be used to generate target impedance ranges for different layers, making sure to take into account the manufacturing tolerances and adjacent wiring provided by the manufacturer.

In the ideal case of signal integrity, all high-speed nodes should be routed in the inner layer of impedance control (such as stripline), but in practice, engineers must often use the outer layer for routing all or part of the high-speed nodes. To optimize the SI and keep the board decoupled, the ground plane/power plane should be placed in pairs as much as possible. If you only have a pair of ground plane/power planes, you will only be there. If there is no power layer at all, you may encounter SI problems by definition. You may also encounter situations where it is difficult to simulate or simulate the performance of a board before the return path of the signal is defined.

4. Crosstalk and impedance control

Coupling from adjacent signal lines will cause crosstalk and change the impedance of the signal lines. Coupling analysis of adjacent parallel signal lines may determine the "safe" or expected spacing (or parallel routing length) between signal lines or between various types of signal lines. For example, to limit the crosstalk of the clock to the data signal node to within 100mV, but to keep the signal traces parallel, you can find the minimum allowable spacing between the signals on any given wiring layer by calculation or simulation. Also, if the design contains nodes with important impedances (either clocks or dedicated high-speed memory architectures), you must place the traces on one layer (or layers) to get the desired impedance.

5. Important high speed nodes

Delay and skew are key factors that must be considered for clock routing. Because of the tight timing requirements, such nodes typically must use termination devices to achieve the best SI quality. These nodes are pre-determined, and the time required to adjust component placement and routing is planned to adjust the pointer for signal integrity design.

6. Technology selection

Different drive technologies are suitable for different tasks. Is the signal point-to-point or point-to-multiple? Is the signal output from the board or on the same board? What is the allowed time lag and noise margin? As a general guideline for signal integrity design, the slower the conversion speed, the better the signal integrity. There is no reason for the 50MHZ clock to have a 500PS rise time. A 2-3NS slew rate control device is fast enough to guarantee the quality of the SI and to help solve problems such as output synchronous switching (SSO) and electromagnetic compatibility (EMC).

The advantages of drive technology can be found in new FPGA programmable technologies or user-defined ASICs. With these custom (or semi-custom) devices, you have a lot of room to choose the drive amplitude and speed. At the beginning of the design, the FPGA (or ASIC) design time is required to meet the appropriate output choices and, if possible, pin selection.

At this stage of design, a suitable simulation model is obtained from the IC supplier. In order to effectively cover the SI simulation, you will need an SI simulation program and the corresponding simulation model (probably the IBIS model).

Finally, during the pre-wiring and routing phases you should create a series of design guidelines that include: target layer impedance, routing spacing, device technology that is preferred, critical node topology, and termination planning.

7. Pre-wired stage

The basic process of pre-wiring SI planning is to first define the input parameter range (drive amplitude, impedance, tracking speed) and possible topological range (min/max length, short line length, etc.), then run each possible simulation combination, analyze the timing and SI simulation results, finally find an acceptable range of values.

Next, the working range is interpreted as the wiring constraints of the PCB layout. This type of "cleaning" preparation can be performed using different software tools, and the routing program can automatically handle such wiring constraints. For most users, timing information is actually more important than SI results, and the results of the interconnect simulation can change the routing to adjust the timing of the signal path.

In other applications, this process can be used to determine the placement of pins or devices that are not compatible with system timing pointers. At this point, it is possible to completely determine the nodes that need to be manually routed or the nodes that do not need to be terminated. For programmable devices and ASICs, the choice of output driver can also be adjusted at this point to improve the SI design or avoid discrete termination devices.

8. Post-wiring SI simulation

In general, the SI design guidelines are difficult to ensure that no SI or timing issues occur after the actual cabling is completed. Even if the design is guided by the guide, unless you can continue to automatically check the design, there is no guarantee that the design will fully comply with the guidelines, so problems will inevitably occur. Post-wiring SI simulation checks will allow for planned breaks (or changes) in design rules, but this is only necessary for cost considerations or strict wiring requirements.

9. Post-production phase

Taking the above measures can ensure the SI design quality of the board. After the board assembly is completed, it is still necessary to place the board on the test platform, using an oscilloscope or TDR (time domain reflectometer) to measure the real board and simulation expectations. The results were compared. These measurements help you improve your model and manufacturing parameters so you can make better (less constraints) decisions in your next pre-design survey.

10. Model selection

There are many articles on model selection, and engineers who have static timing verification may have noticed that although it is possible to obtain all the data from the device data table, it is still difficult to build a model. The SI simulation model is just the opposite. The model is easy to build, but the model data is difficult to obtain. Essentially, the only reliable source of SI model data is the IC supplier, who must maintain a tacit understanding with the design engineer. The IBIS model standard provides a consistent data carrier, but the establishment of the IBIS model and the guarantee of its quality are costly. IC suppliers still need market demand for this investment, and circuit board manufacturers may be the only demanders. market.