Designing Signal Integrity Analysis for High Speed ​​Circuits

To perform an integrity analysis of a signal, you first need to build an accurate device model. In the past, the SPICE model was widely used in circuit simulation. It is based on the working mechanism and physical details of the basic components of the circuit (such as transistors, resistors, capacitors, etc.), and can accurately simulate the operating characteristics of the system at the level of the circuit device. To verify the logic function of the system, it has been widely used in integrated circuit design. Because it can accurately calculate various operating characteristics such as static and dynamic of the system, it can also be used for system-level signal integrity analysis. However, there are some insurmountable shortcomings in using the SPICE model: First, since the SPICE model is a transistor-level model, as the size of integrated circuits becomes larger and larger, even if only the SPICE model of each pin is established, it will contain thousands of 10,000 transistor level one device, so its simulation speed must be very slow, which is unacceptable for interactive PCB design; secondly, because the SPICE model involves many details of integrated circuit design, general IC manufacturers are not willing Public offering limits its wide range of embarrassment. I need another generic model to replace the SPICE model to complete the signal integrity analysis. The IBIS model is generated in this case. The IBIS model describes the input and output (I/O) characteristics of individual device pins through a family of current/voltage (I/V) and voltage/time (V/T) curves. Since the IBIS model only describes the external characteristics of the device, does not involve the internal details of the device, and does not have the problem of intellectual property leakage, so the technology of the major integrated circuit manufacturers has been obtained. In addition, the abstraction level of the IBIS model is higher than that of the SPICE model. It is a model built on the device level. The amount of calculation required for simulation is small, so the simulation speed is greatly improved. Generally, it is two orders of magnitude higher than the SPICE model, which is very suitable for the system level. Simulation. Now the IBIS model has been accepted as the international standard EIA/ANSI-656, and the version has also evolved from ver1.0 to the current ver3.2.

1. Composition of the IBIS model

The basic principle of IBIS modeling is introduced below by taking the CMOS circuit input/output buffer as an example. For modeling other devices, refer to the IBIS specification.

1.1 Input model

The input buffer model includes the main factors that affect the quality of the signal transmission. C_pkg, R_pkg, and L_pkg are the package parameters of the pin, respectively corresponding to the parasitic capacitance, resistance and inductance caused by the package; C_comp is the input capacitance of the leg, which is determined by the content structure of the device; Power_Clamp and GND_Clamp respectively represent the input clamp of the leg Bit diodes whose characteristics are described by the input current/voltage (I/V) curve.

1.2 Output model

The output model is slightly more complicated than the input model. C_pkg, R_pkg, L_pkg are still the package parameters of the leg; C_comp is the output capacitance of the leg, and Power_Clamp and GND_Clamp respectively represent the output clamp diode of the leg, and its characteristics are also described by the V/I curve; unlike the input, The Pullup and Pulldown parameters are added to the output model. Pullup indicates the relationship between the same pull-up voltage and the output current when the output is high. The meaning of Pulldown is the opposite. They are all described by the V/I curve. Ramp_rate indicates the rate of change of the output voltage. This is a dynamic parameter that describes the AC characteristics of the device.

1.3 Representation of the IBIS model

Like the SPICE model, IBIS model files are also represented in readable ASCII code. The IBIS model of a device consists of several parts, each beginning with a keyword and then using the data or table form for the defined keywords. description. Below is an example of a simple IBIS model file that includes some of the most commonly used keywords:

[IBIS Ver] 2.1

[Comment Char] |_char

[File Name] n74f244n.ibs

[File Rev] 2.0

[Date] September 17,1997

[Source] File originated at Intel Corporation, as an example of an IBIS Version 1.0 file.

[Notes] This is modified from an original Version 1.0 example to include some IBIS Version 2.1 features to check some keywords,sub parameters and IBIS format style.

[Disclaimer] This information is for modeling purposes only, and is not guaranteed.

[Copyright] None

[Component] N74F244N

[Manufacturer] Philips

[Package]

| typ min max

R_pkg 50m 10m 100m

L_pkg 6.3nH 2.4nH 10.2nH

C_pkg 1.35pF 0.89pF 1.81pF

|

[Pin] signal_name model_name R_pin L_pin C_pin

|

1 Oea# ENABLE NA 10.2nH 1.81pF

2 Ia0 F244_INP NA 7.8nH 1.50pF

3 Yb0 F244_OUT NA 5.8nH 1.17pF

... data omitted ...

20 Vcc POWER NA 10.2nH 1.81pF

| F244_OUT MODEL

[Model] F244_OUT

Model_type 3-state

Polarity Non-Inverting

Enable Active-Low

Rref = 500

Cref = 50pF

Vref = 0V

Vmeas = 1.5V

| typ min max

[Voltage Range] 5.0V 4.5V 5.5V

[Pulldown]

| Voltage I(typ) I(min) I(max)

-5.0V -16m -15.2m -16.5m

-4.0V -14m -13.2m -14.5m

... data omitted ...

10.0V 755m 612m 810m

[Pullup]

... data omitted ...

[GND Clamp]

| Voltage I(typ) I(min) I(max)

-5.0V -784m -756m -811m

-1.0V -64m -56m -71m

... data omitted ...

5.0V 0.0m 0.0m 0.0m

[Ramp]

| typ min max

dV/dt_r 1.5/2.00n 1.5/2.98n 1.5/1.61n

dV/dt_f 2.0/1.21n 2.0/1.74n 2.0/0.65n

| F244_INP MODEL

... data omitted ...

| ENABLE MODEL

... data omitted ...

|

[End]

The IBIS model can be provided by the IC manufacturer, or it can be measured by actual measurement, or the existing SPICE model can be converted. Now there are many mature conversion programs available.

2. IBIS model accuracy

Since the IBIS model is a result of SPICE model conversion or direct measurement, it has high precision and can well reflect the external characteristics of the device.

The circuit uses an output buffer to drive a section of the transmission line load and measure the voltage waveform at the end of the transmission line.

The simulation results of the two methods are similar, so the signal integrity analysis using the IBIS model is very accurate and reliable.