Design Model of High Speed Digital PCB Based on Signal Integrity Analysis

How to fully consider the signal integrity factors in the PCB design process and take effective control measures has become a hot topic in the PCB design industry today. The high-speed digital PCB board design method based on signal integrity computer analysis can effectively achieve the signal integrity of PCB design.

1. Overview of signal integrity issues

Signal Integrity (SI) is the ability of a signal to respond in the circuit with the correct timing and voltage. If the signal in the circuit can reach the IC with the required timing, duration, and voltage amplitude, the circuit has better signal integrity. Conversely, when the signal does not respond properly, a signal integrity problem occurs. Broadly speaking, signal integrity problems are mainly manifested in five aspects: delay, reflection, crosstalk, synchronous switching noise (SSN) and electromagnetic compatibility (EMI).

Delay means that the signal is transmitted at a limited speed on the wires of the PCB board, and the signal is sent from the transmitting end to the receiving end with a transmission delay. The delay of the signal affects the timing of the system. In high-speed digital systems, the propagation delay depends primarily on the length of the wire and the dielectric constant of the medium surrounding the wire.

In addition, when the characteristic impedance of the wire on the PCB (called the transmission line in the high-speed digital system) does not match the load impedance, a part of the energy will be reflected back along the transmission line after the signal reaches the receiving end, causing the signal waveform to be distorted or even appearing. Overshoot and undershoot. If the signal is reflected back and forth on the transmission line, ringing and surround oscillations will occur.

Since there is mutual capacitance and mutual inductance between any two devices or wires on the PCB, when the signal on one device or one wire changes, the change will affect other devices through mutual capacitance and mutual inductance. Wire, which is crosstalk. The strength of the crosstalk depends on the geometry and mutual distance of the device and the wires.

When many digital signals on the PCB are switched synchronously (such as the CPU's data bus, address bus, etc.), due to the impedance on the power and ground lines, synchronous switching noise will occur, and ground level bounce will occur on the ground. Noise (referred to as ground bounce). The strength of the SSN and ground bounce also depends on the IO characteristics of the integrated circuit, the impedance of the PCB board power plane and ground plane, and the layout and routing of high speed devices on the PCB.

In addition, like other electronic devices, PCBs also have electromagnetic compatibility problems, and their generation is mainly related to the layout and wiring of PCB boards.

2. Signal Integrity Analysis Model

The core part of the PCB design method based on signal integrity computer analysis is the establishment of the PCB board level signal integrity model, which is the difference from the traditional design method.

The correctness of the SI model will determine the correctness of the design, and the establishability of the SI model determines the feasibility of this design method.

2.1. SI model for PCB design

There are a number of models in electronic design that can be used for PCB board level signal integrity analysis. The three most commonly used are SPICE, IBIS and Verilog-A.

a. SPICE model

SPICE is a powerful general purpose analog circuit simulator. The SPICE model has been widely used in electronic design, and two major versions have been derived: HSPICE and PSPICE. HSPICE is mainly used in integrated circuit design, while PSPICE is mainly used in PCB board and system level design.

The SPICE model consists of two parts: Model Equations and Model Parameters. Since the model equations are provided, the SPICE model can be closely coupled with the simulator's algorithm to achieve better analysis efficiency and analysis results.

When using the SPICE model for SI analysis at the PCB level, integrated circuit designers and manufacturers are required to provide detailed and accurate descriptions of the SPICE model and semiconductor characteristics of the integrated circuit I/O unit sub-circuit. Since these materials are usually intellectual property and confidentiality of designers and manufacturers, only a small number of semiconductor manufacturers will provide the corresponding SPICE models while providing chip products.

The accuracy of the SPICE model analysis depends mainly on the source of the model parameters (ie, the accuracy of the data) and the scope of application of the model equations. The combination of model equations with various digital simulators may also affect the accuracy of the analysis. In addition, the SPICE model of the PCB board level has a large amount of simulation calculation, and the analysis is time consuming.

b. IBIS model

The IBIS model was originally developed by Intel Corporation as a model for digital signal integrity analysis for PCB board and system level. It is now managed by the IBIS Open Forum and has become the official industry standard (EIA/ANSI 656-A).

The IBIS model uses I/V and V/T tables to describe the characteristics of digital integrated circuit I/O cells and pins. Since the IBIS model does not need to describe the internal design of the I/O unit and the transistor manufacturing parameters, it is welcomed and supported by semiconductor manufacturers. Now major digital IC manufacturers are able to provide the corresponding IBIS models while providing chips.

The accuracy of the analysis of the IBIS model depends mainly on the number of data points and the accuracy of the data in the I/V and V/T tables. Since the board level simulation based on the IBIS model uses table lookup calculation, the calculation amount is small, usually only 1/10 to 1/100 of the corresponding SPICE model.

c. Verilog-AMS model and VHDL-AMS model

Verilog-AMS and VHDL-AMS have been around for less than four years and are a new standard. As a hardware behavioral modeling language, Verilog-AMS and VHDL-AMS are supersets of Verilog and VHDL, respectively, while Verilog-A is a subset of Verilog-AMS.

Unlike the SPICE and IBIS models, the AMS language is written by the user to describe the behavior of the component. Similar to the IBIS model, the AMS modeling language is a stand-alone model format that can be applied to many different types of simulation tools. The AMS equation can also be written at many different levels: transistor level, I/O unit level, I/O unit group, and more.

Since Verilog-AMS and VHDL-AMS are a new standard, only a few semiconductor manufacturers have been able to provide AMS models so far, and there are fewer simulators that can support AMS than SPICE and IBIS. However, the feasibility and accuracy of the AMS model in PCB board-level signal integrity analysis are not inferior to the SPICE and IBIS models.

2.2 Model selection

Since there is currently no unified model to perform all PCB-level signal integrity analysis, in high-speed digital PCB design, it is necessary to mix the above models to maximize the transmission model of key signals and sensitive signals.

For discrete passive components, you can seek out the SPICE model provided by the manufacturer, or directly establish and use a simplified SPICE model through experimental measurements.

For critical digital integrated circuits, the IBIS model provided by the manufacturer must be sought. Most integrated circuit design and manufacturers are currently able to provide the required IBIS models while providing chips through a Web site or other means.

For non-critical integrated circuits, if the manufacturer's IBIS model is not available, a similar or default IBIS model can be selected based on the function of the chip pins. Of course, a simplified IBIS model can also be established by experimental measurements.

For the transmission line on the PCB board, a simplified transmission line SPICE model can be used for signal integrity pre-analysis and solution space analysis, and in the post-layout analysis, the complete transmission line SPICE model needs to be used according to the actual layout design.