Pre PCB Layout Checklist

1. Prepare Documents

● Verified schematics including and net-list.

● Confirmed BOM file complete with manufacturer part numbers (MPN), and where libraries are missing, datasheets including land pattern data.

● Provide the basic PCB layout and identify the location of important units and circuits.

● Provide mechanical details of the PCB including the PCB outline, mounting holes, placing of important components, keep-out areas and other related information.

2. Layout Checklist

● High-current components and networks with a current of 1A or greater.

● Important clock signals, differential signals, and high-speed digital signals.

● Analog signals and other signals that are susceptible to interference.

● Other signals with special requirements.

● Differential distribution lines, shielded networks, characteristic impedance networks, equal delay networks, etc.

● Electrical keep-out areas, special solder paste and solder mask openings, and other special requirements.

● Ensure the schematic is fully understood and that circuit architecture and the operating conditions of the networks are known.

● Confirm the critical networks in the PCB and understand the design requirements for high-speed components.

Design Process

1. Determine Component Package

● Ensure the packages and footprints of all components are available in the component library of the chosen EDA tool and are correct.  

● All information in the network table is capitalized to avoid loading problems or discontinuity in the PCB BOM.

● Specific naming of the components and the company's specifications should be unified.

2. Establish the Board Outline

● Create the board layout according to the PCB mechanical diagram, or use the corresponding template including mounting holes, keep-out areas and other features.

3. Import the Net List

● Import the network table into the chosen EDA software. Since the process is different for different software, please refer to the specific EDA’s documentation for instructions.

● It is suggested to import the netlist at least twice to ensure no errors have occurred in the importing process.

4. PCB Layout

● First set the design origin. Generally, the design origin is set at the intersection of the left and bottom sides of the design, or the first through-hole pad.

● Once the origin has been determined, component layout and wiring are referenced to this point. A 10-25 mil grid is recommended for PCB layout.

● Place components with specific location requirements and lock them into place to prevent accidental adjustment.

● PCB Layout Basic Principles

1. Prioritize the layout of components with special requirements and occupy more board space.
2. Layout important components along the direction of the signal. 
3. Keep signal traces short, especially key signal lines.
4. Separate strong and weak signals, high and low voltage signals.
5. Enough space should be left for high-frequency components.
6. Separate analog and digital signals.

● Maintain layout symmetry for similar circuits where possible.

● The general layout should be evenly distributed with a balanced center of gravity where possible.

● Components should be placed in a way that facilitates debugging and maintenance. Tall components should not be spaced next to shorter parts, and sufficient spacing should be left between components, especially those involved in debugging.

● Components of the same type should be aligned in the same direction, especially polarized components of the same type to assist orientation and prevent errors.

● Heat-generating components should have enough space for heat dissipation and heat-sensitive components should be kept away from heat-generating components. At the same time, consider the direction of airflow within the enclosure during normal operating conditions and its heat-dissipating effects.

● As a general rule, dual in-line components should be separated from each other by more than 2 mm. BGA parts should be separated from adjacent components by more than 5 mm and the distance between chip resistors and capacitors, and other small SMD components should be greater than 0.7 mm.

● The distance between two pads of SMD components should be more than 2 mm.

● Do not place original cartridge devices within 5 mm of a crimped component.

● Do not place SMD components within 5 mm of the soldering surface.

● Decoupling capacitors should be located as close as possible to the power supply pin of the IC, with priority given to higher frequency signals. Reduce the path length from the power supply to ground as much as possible. 

● Bypass capacitors should be evenly distributed around the respective IC.

● When laying out components, consider placing components that use the same power supply together.

● The placement of resistors and capacitors for impedance matching purposes should be arranged reasonably according to their properties and purposes.

a. The layout of matching capacitors and resistors should be clearly defined. For terminal matching for multiple loads, the capacitors and resistors should be placed at the farthest end.

b. Matching resistors should be close to the driving end of the signal. The distance generally should not be greater than 500 mil.

● Optimize Text Layout 

a. Text such as part designators should not be placed on top of solder pads, as it will be removed during PCB manufacture or covered after soldering.

b. Ensure all designators and important text are visible after the assembly of all components. The text should be in the same orientation, font, and size where possible.

● Place the relevant fiducials on the PCB to assist assembly of hard-to-place components and on breakaway rails if present.

5. PCB Wiring

● Prioritization:

a. Low-Density Prioritization: Start routing the devices with the simplest connections and lowest densities.

b. Core Component Prioritization: Route core parts such as DDR and RAM first. Similar signals should are routed with similar signal, power and ground loops. Other inferior signals should not interfere with key signals.

c. Key Signal Prioritization: Wiring power supply, analog small signals, high-speed signals, clock signals, synchronization signals and other key signals first.

● Ground loop rules:

The signal trace and loop should be as small as possible to decrease radiation, thereby reducing interference. 

When dividing the ground plane signal alignment should be considered to avoid crossing the ground plane split.

For double-layer boards, leave enough space for a power supply and fill the remaining area with a ground reference plane, and add vias to connect signals on the two sides.

For high-frequency designs, extra attention should be paid to ground plane design and it is recommended to use multilayer boards.

● Reducing Interference:

Long parallel wiring between different networks on the PCB may incur mutual interference. To avoid this, increase the spacing between traces and use 3W rule for trace spacing.

● Alignment direction control rules:

Route traces in adjacent layers orthogonally to reduce different signals running parallel to each other, thereby reducing inter-layer crosstalk.

● Impedance matching rules:

Maintain consistent trace width along the length of a signal. Changes in line width will cause uneven characteristic impedance since the high transmission speed will produce reflections which should be avoided. Under certain conditions, such as traces leading to connectors, it may be impossible to avoid changes in line width. The best way is to minimize the effective length of changed lines.

● Right angle/acute angle routing rules:

Avoid acute and right angles in high-speed PCB design to minimize impedance change. Trace-to-trace connections should be should be ≥ 135° or rounded.

● Integrity rules for power and ground layers:

For areas with densely packed vias, avoid arranging in them in such a way that the antipads would break up or divide the plane. Breaking up the plane can destroy the signal integrity of the plane and increase in the length of the return path.

● 3W Rule:

Parallel traces should follow the 3W rule, where traces should be spaced at least 3 times the width of the trace away from each other, measured from the center of the traces. Doing so reduces coupling and can reduce the crosstalk by 70%. To increase this to 98%, a 10W rule can be applied

● 20H rule:

Since the electric field between the power supply layer and the ground layer is variable, electromagnetic interference radiates out at the edges of the board. It is possible to shrink the power plane inwards so that the electric field is conducted only within the confines of the ground layer. Taking one H (thickness of dielectric between power and ground) as a unit, if the inward shrinkage is 20H, 70% of the electric field can be confined within the edges of the ground plane. To raise this figure to 98%, 100H can be implemented.

Setting rules

1. Board Stack-up Considerations

● In high-speed digital circuits, power and ground planes should be kept adjacent to each other if possible, with no signal layer in between.

If orthogonal signal routing between adjacent layers cannot be implemented, avoid overlapping parallel signals as much as possible.

Choose a stack-up to according to the impedance requirements of the design. Position reference layers accordingly and place signals with impedance requirements on the impedance-controlled layers.

2. Choosing trace width and trace spacing

● When the average current of the signal is relatively large, it is necessary to consider the relationship between the line width and the current. Please refer to the following table.

3. Choosing via diameter

● The following table can be used to select via diameters and annular ring sizes.