High speed converter PCB design

What are the important PCB layout rules when using high-speed converters?

In order to ensure that the design performance meets the technical specifications of the data sheet, some guidelines must be observed. First of all, there is a common question: "AGND and DGND ground should be separated?" The simple answer is: as the case may be.

The detailed answer is: usually not separated. Because in most cases, separating the ground plane will only increase the inductance of the return current, it will bring more harm than good. From the formula V = L(di/dt), it can be seen that the voltage noise increases as the inductance increases. As the switch current increases (since the converter sampling rate increases), the voltage noise also increases. Therefore, the ground plane should be connected together.

An example is that, in some applications, in order to comply with the traditional design requirements, dirty bus power or digital circuits must be placed in certain areas, and also affected by size constraints, so that the circuit board can not achieve a good layout segmentation. In this case, separating the ground plane is the key to good performance. However, for the overall design to be effective, these ground planes must be connected together somewhere in the board through a bridge or connection point. Therefore, the connection points should be evenly distributed on separate ground planes. Ultimately, there is often a connection point on the PCB that is the best place to return current through without causing performance degradation. This connection point is usually located near or below the converter.

When designing the power plane, all copper wires that can be used in these layers should be used. If possible, do not allow these layers to share traces because extra traces and vias will divide the power plane into smaller pieces that can quickly damage the power plane. The resulting sparse power plane can squeeze the current path to where these paths are most needed, ie, the power pins of the converter. Squeezing the current between the via and the trace increases the resistance, causing a slight voltage drop on the power supply pin of the converter.

Finally, the placement of the power plane is critical. Do not layer the high-noise digital power supply on the analog power plane, otherwise the two may be coupled even though they are in different layers. In order to minimize the risk of system degradation, these types of layers should be separated as much as possible in the design rather than stacked together.

At the same time, the task of discussing the design of transmission systems (PDS) for printed circuit boards (PCBs) is often overlooked, but it is crucial for system-level analog and digital designers.

The design goal of the PDS (Power Transmission System) is to minimize voltage ripple generated in response to supply current demand. All circuits need current, some circuits require more, and some circuits need to provide current at a faster rate. With fully decoupled, low-impedance power planes or ground planes, and good PCB stackup, voltage ripple due to circuit current demand can be minimized. For example, if the designed switching current is 1A and the impedance of the PDS is 10mΩ, the maximum voltage ripple is 10mV.

First, a PCB stack structure that supports larger layer capacitors should be designed. For example, a six-layer stack may include a top signal layer, a first ground plane, a first power plane, a second power plane, a second ground plane, and a bottom signal layer. It is specified that the first ground layer and the first power layer are close to each other in the stacked structure, and the two layers have a pitch of 2 to 3 mils to form an inherent layer capacitance. The biggest advantage of this capacitor is that it is free, just specify in the PCB manufacturing notes. If you have to split the power plane and there are multiple VDD power rails on the same layer, use as large a power plane as possible. Do not leave holes, but also pay attention to sensitive circuits. This will maximize the capacitance of the VDD layer. If the design allows the presence of additional layers (in this case from six to eight layers), two additional ground planes should be placed between the first and second power planes. In the case where the core pitch is also 2 to 3 mils, the intrinsic capacitance of the laminated structure will double at this time.

For an ideal PCB stackup, decoupling capacitors should be used around the initial entry point of the power plane and around the DUT, which will ensure that the PDS impedance is low over the entire frequency range. Using several 0.001μF to 100μF capacitors helps cover this range. It is not necessary to configure the capacitors everywhere; the connection of capacitors to the DUT will destroy all manufacturing rules. If such drastic measures are needed, there are other problems with the circuit.